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| UC1573 UC2573 UC3573 Buck Pulse Width Modulator Stepdown Voltage Regulator FEATURES * * * * * Simple Single Inductor Buck PWM Stepdown Voltage Regulation Drives External PMOS Switch Contains UVLO Circuit Includes Pulse-by-Pulse Current Limit Low 50A Sleep Mode Current DESCRIPTION The UC3573 is a Buck pulse width modulator which steps down and regulates a positive input voltage. The chip is optimized for use in a single inductor buck switching converter employing an external PMOS switch. The block diagram consists of a precision reference, an error amplifier configured for voltage mode operation, an oscillator, a PWM comparator with latching logic, and a 0.5A peak gate driver. The UC3573 includes an undervoltage lockout circuit to insure sufficient input supply voltage is present before any switching activity can occur, and a pulse-by-pulse current limit. Input current can be sensed and limited to a user determined maximum value. In addition, a sleep comparator interfaces to the UVLO circuit which turns the chip off when the input voltage is below the UVLO threshold. This reduces the supply current to only 50A, making the UC3573 ideal for battery powered applications. BLOCK DIAGRAM UDG-94106-1 6/98 UC1573 UC2573 UC3573 ABSOLUTE MAXIMUM RATINGS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35V EAINV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.6V to VCC IEAOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 4V CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7A to 0.7A I3VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-15mA Storage Temperature . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . .+300C Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. CONNECTION DIAGRAMS DIL-8, SOIC-8 (TOP VIEW) J or N, D Packages ELECTRICAL CHARACTERISTICS Unless otherwise stated, these parameters apply for TA = -55C to +125C for the UC1573, -40C to +85C for the UC2573, and 0C to +70C for the UC3573, VCC = 5V, CT = 680pF, TA = TJ. PARAMETER Reference Section 3VREF Line Regulation Load Regulation Oscillator Section Frequency Error Amp Section EAINV IEAINV AVOL EAOUT High EAOUT Low IEAOUT Unity Gain Bandwidth Current Sense Comparator Section Threshold (referred to VCC) Input Bias Current CS Propagation Delay Gate Drive Output Section OUT High Saturation TEST CONDITION MIN 2.94 VCC = 4.75 to 30V I3VREF = 0 to -5mA VCC = 5V, 30V EAOUT = 2V EAOUT = 2V EAOUT = 0.5V to 3V EAINV = 1.4V EAINV = 1.6V EAINV = 1.4V, EAOUT = 2V EAINV = 1.6V, EAOUT = 2V TJ = 25C, F = 10kHz 85 1.45 65 3.6 -350 7 0.6 -0.39 CS = VCC TYP 3 1 1 100 1.5 -0.2 90 4 0.1 -500 20 1 -0.43 150 400 0 0.7 1.5 0.1 1.5 30 30 92 25 3.5 100 35 4.2 200 MAX UNITS 3.06 10 10 115 1.55 -1 4.4 0.2 V mV mV kHz V A dB V V A mA MHz V nA ns V V V V V ns ns % % %/V V mV -0.47 800 OUT Low Saturation Rise Time Fall Time Pulse Width Modulator Section Maximum Duty Cycle Minimum Duty Cycle Modulator Gain Undervoltage Lockout Section Start Threshold Hysteresis IOUT = 0 IOUT = -10mA IOUT = -100mA IOUT = 10mA IOUT = 100mA TJ = 25C, CLOAD = 1nF + 3.3 Ohms TJ = 25C, CLOAD = 1nF + 3.3 Ohms EAINV = 1.4V EAINV = 1.6V EAOUT = 1.5V to 2.5V 0.3 1.5 2.5 0.4 2.2 80 80 96 0 45 4.5 300 2 UC1573 UC2573 UC3573 ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these parameters apply for TA = -55C to +125C for the UC1573, -40C to +85C for the UC2573, and 0C to +70C for the UC3573, VCC = 5V, CT = 680pF, TA = TJ. PARAMETER Sleep Mode Section Threshold Supply Current Section IVCC IVCC TEST CONDITION MIN 1.8 VCC = 30V VCC = 30V, EAINV = 3V TYP 2.2 9 50 MAX UNITS 2.6 12 150 V mA A PIN DESCRIPTIONS 3VREF: Precision 3V reference. Bypass with 100nF capacitor. CS: Peak current limit sense pin. Senses the current across a current sense resistor placed between VCC and source of the PMOS Buck switch. OUT will be held high (PMOS buck switch off) if VCC - CS exceeds 0.4V. EAINV: Inverting input to error amplifier. VOUT sense feedback connected to this pin. The non-inverting input of the error amplifier is internally connected to 3VREF volts. 2. Connecting the EAINV pin to an external voltage greater than 2.6V commands the chip to go into a low current sleep mode. EAOUT: Output of error amplifier. Use EAOUT and EAINV for loop compensation components. GND: Circuit Ground. OUT: Gate drive for external PMOS switch connected between VCC and the flyback inductor. OUT drives the gate of the PMOS switch between VCC and GND. RAMP: Oscillator and ramp for pulse width modulator. Frequency is set by a capacitor to GND by the equation 1 F= 15k CRAMP Recommended operating frequency range is 10kHz to 200kHz. * VCC: Input voltage supply to chip. Range is 4.75V to 30V. Bypass with a 1F capacitor. UDG-94107 Typical Waveforms 3 UC1573 UC2573 UC3573 TYPICAL APPLICATION: 12V TO 5V BUCK CONVERTER UDG-94108-1 UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460 4 |
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